An Accurate 0.55-V 2.6-μW Voltage-Level Detector

Asaf Feldman, Joseph Shor

Research output: Contribution to journalArticlepeer-review

Abstract

A CMOS voltage-level detector (VLD) circuit is proposed for Internet-of-Things systems which operates near the minimum energy point. It can accurately detect VCC levels of 550-640 mV, making it one of the lowest voltage VLDs reported to date. A novel pull-up circuit is utilized to accurately detect fast V CC ramps of 10's of microseconds, which are faster than the power-up of the VLD itself. This feature enables it to operate at a low power consumption of 2.6 uW. A low voltage, charge-pumped bandgap reference is utilized with a highly accurate comparator to achieve a 35-mV variation across temperature and a random variation sigma of 1.68 mV. This circuit is one of the lowest voltage, most highly accurate, and fastest ramp-detect VLDs that have been reported in the literature.

Original languageEnglish
Article number9129800
Pages (from-to)166-169
Number of pages4
JournalIEEE Solid-State Circuits Letters
Volume3
DOIs
StatePublished - 2020

Keywords

  • Bandgap
  • CMOS
  • Power-Good
  • SoC
  • power management
  • voltage-level detector (VLD)

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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