Accelerating inference on binary neural networks with digital rram processing

João Vieira; Edouard Giacomin; Yasir Qureshi; Marina Zapater; Xifan Tang; Shahar Kvatinsky; David Atienza; Pierre Emmanuel Gaillardon

doi:10.1007/978-3-030-53273-4_12

Accelerating inference on binary neural networks with digital rram processing

João Vieira, Edouard Giacomin, Yasir Qureshi, Marina Zapater, Xifan Tang, Shahar Kvatinsky, David Atienza, Pierre Emmanuel Gaillardon

Electrical and Computer Engineering

Technion - Israel Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Chapter › peer-review

Abstract

The need for efficient Convolutional Neural Network (CNNs) targeting embedded systems led to the popularization of Binary Neural Networks (BNNs), which significantly reduce execution time and memory requirements by representing the operands using only one bit. Also, due to 90% of the operations executed by CNNs and BNNs being convolutions, a quest for custom accelerators to optimize the convolution operation and reduce data movements has started, in which Resistive Random Access Memory (RRAM)-based accelerators have proven to be of interest. This work presents a custom Binary Dot Product Engine(BDPE) for BNNs that exploits the low-level compute capabilities enabled RRAMs. This new engine allows accelerating the execution of the inference phase of BNNs by locally storing the most used kernels and performing the binary convolutions using RRAM devices and optimized custom circuitry. Results show that the novel BDPE improves performance by 11.3%, energy efficiency by 7.4% and reduces the number of memory accesses by 10.7% at a cost of less than 0.3% additional die area.

Original language	English
Title of host publication	VLSI-SoC
Subtitle of host publication	New Technology Enabler - 27th IFIP/IEEE WG 10.5 International Conference on Very Large Scale Integration, VLSI-SoC 2019, Revised and Extended Selected Papers
Editors	Carolina Metzler, Ricardo Reis, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Carlos Silva-Cardenas
Chapter	12
Pages	257-278
Number of pages	22
DOIs	https://doi.org/10.1007/978-3-030-53273-4_12
State	Published - 2020
Event	27th IFIP/IEEE WG 10.5 International Conference on Very Large Scale Integration, VLSI-SoC 2019 - Cusco, Peru Duration: 6 Oct 2019 → 9 Oct 2019

Publication series

Name	IFIP Advances in Information and Communication Technology
Volume	586 IFIP

Conference

Conference	27th IFIP/IEEE WG 10.5 International Conference on Very Large Scale Integration, VLSI-SoC 2019
Country/Territory	Peru
City	Cusco
Period	6/10/19 → 9/10/19

Keywords

Binary Neural Networks
Embedded systems
Machine Learning
RRAM-based Binary Dot Product Engine

All Science Journal Classification (ASJC) codes

Information Systems
Computer Networks and Communications
Information Systems and Management

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1007/978-3-030-53273-4_12

Cite this

Vieira, J., Giacomin, E., Qureshi, Y., Zapater, M., Tang, X., Kvatinsky, S., Atienza, D., & Gaillardon, P. E. (2020). Accelerating inference on binary neural networks with digital rram processing. In C. Metzler, R. Reis, P.-E. Gaillardon, G. De Micheli, & C. Silva-Cardenas (Eds.), VLSI-SoC: New Technology Enabler - 27th IFIP/IEEE WG 10.5 International Conference on Very Large Scale Integration, VLSI-SoC 2019, Revised and Extended Selected Papers (pp. 257-278). (IFIP Advances in Information and Communication Technology; Vol. 586 IFIP). https://doi.org/10.1007/978-3-030-53273-4_12

Vieira, João ; Giacomin, Edouard ; Qureshi, Yasir et al. / Accelerating inference on binary neural networks with digital rram processing. VLSI-SoC: New Technology Enabler - 27th IFIP/IEEE WG 10.5 International Conference on Very Large Scale Integration, VLSI-SoC 2019, Revised and Extended Selected Papers. editor / Carolina Metzler ; Ricardo Reis ; Pierre-Emmanuel Gaillardon ; Giovanni De Micheli ; Carlos Silva-Cardenas. 2020. pp. 257-278 (IFIP Advances in Information and Communication Technology).

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title = "Accelerating inference on binary neural networks with digital rram processing",

abstract = "The need for efficient Convolutional Neural Network (CNNs) targeting embedded systems led to the popularization of Binary Neural Networks (BNNs), which significantly reduce execution time and memory requirements by representing the operands using only one bit. Also, due to 90% of the operations executed by CNNs and BNNs being convolutions, a quest for custom accelerators to optimize the convolution operation and reduce data movements has started, in which Resistive Random Access Memory (RRAM)-based accelerators have proven to be of interest. This work presents a custom Binary Dot Product Engine(BDPE) for BNNs that exploits the low-level compute capabilities enabled RRAMs. This new engine allows accelerating the execution of the inference phase of BNNs by locally storing the most used kernels and performing the binary convolutions using RRAM devices and optimized custom circuitry. Results show that the novel BDPE improves performance by 11.3%, energy efficiency by 7.4% and reduces the number of memory accesses by 10.7% at a cost of less than 0.3% additional die area.",

keywords = "Binary Neural Networks, Embedded systems, Machine Learning, RRAM-based Binary Dot Product Engine",

author = "Jo{\~a}o Vieira and Edouard Giacomin and Yasir Qureshi and Marina Zapater and Xifan Tang and Shahar Kvatinsky and David Atienza and Gaillardon, {Pierre Emmanuel}",

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year = "2020",

doi = "10.1007/978-3-030-53273-4_12",

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Vieira, J, Giacomin, E, Qureshi, Y, Zapater, M, Tang, X, Kvatinsky, S, Atienza, D & Gaillardon, PE 2020, Accelerating inference on binary neural networks with digital rram processing. in C Metzler, R Reis, P-E Gaillardon, G De Micheli & C Silva-Cardenas (eds), VLSI-SoC: New Technology Enabler - 27th IFIP/IEEE WG 10.5 International Conference on Very Large Scale Integration, VLSI-SoC 2019, Revised and Extended Selected Papers. IFIP Advances in Information and Communication Technology, vol. 586 IFIP, pp. 257-278, 27th IFIP/IEEE WG 10.5 International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco, Peru, 6/10/19. https://doi.org/10.1007/978-3-030-53273-4_12

Accelerating inference on binary neural networks with digital rram processing. / Vieira, João; Giacomin, Edouard; Qureshi, Yasir et al.
VLSI-SoC: New Technology Enabler - 27th IFIP/IEEE WG 10.5 International Conference on Very Large Scale Integration, VLSI-SoC 2019, Revised and Extended Selected Papers. ed. / Carolina Metzler; Ricardo Reis; Pierre-Emmanuel Gaillardon; Giovanni De Micheli; Carlos Silva-Cardenas. 2020. p. 257-278 (IFIP Advances in Information and Communication Technology; Vol. 586 IFIP).

Research output: Chapter in Book/Report/Conference proceeding › Chapter › peer-review

TY - CHAP

T1 - Accelerating inference on binary neural networks with digital rram processing

AU - Vieira, João

AU - Giacomin, Edouard

AU - Qureshi, Yasir

AU - Zapater, Marina

AU - Tang, Xifan

AU - Kvatinsky, Shahar

AU - Atienza, David

AU - Gaillardon, Pierre Emmanuel

N1 - Publisher Copyright: © IFIP International Federation for Information Processing 2020.

PY - 2020

Y1 - 2020

N2 - The need for efficient Convolutional Neural Network (CNNs) targeting embedded systems led to the popularization of Binary Neural Networks (BNNs), which significantly reduce execution time and memory requirements by representing the operands using only one bit. Also, due to 90% of the operations executed by CNNs and BNNs being convolutions, a quest for custom accelerators to optimize the convolution operation and reduce data movements has started, in which Resistive Random Access Memory (RRAM)-based accelerators have proven to be of interest. This work presents a custom Binary Dot Product Engine(BDPE) for BNNs that exploits the low-level compute capabilities enabled RRAMs. This new engine allows accelerating the execution of the inference phase of BNNs by locally storing the most used kernels and performing the binary convolutions using RRAM devices and optimized custom circuitry. Results show that the novel BDPE improves performance by 11.3%, energy efficiency by 7.4% and reduces the number of memory accesses by 10.7% at a cost of less than 0.3% additional die area.

AB - The need for efficient Convolutional Neural Network (CNNs) targeting embedded systems led to the popularization of Binary Neural Networks (BNNs), which significantly reduce execution time and memory requirements by representing the operands using only one bit. Also, due to 90% of the operations executed by CNNs and BNNs being convolutions, a quest for custom accelerators to optimize the convolution operation and reduce data movements has started, in which Resistive Random Access Memory (RRAM)-based accelerators have proven to be of interest. This work presents a custom Binary Dot Product Engine(BDPE) for BNNs that exploits the low-level compute capabilities enabled RRAMs. This new engine allows accelerating the execution of the inference phase of BNNs by locally storing the most used kernels and performing the binary convolutions using RRAM devices and optimized custom circuitry. Results show that the novel BDPE improves performance by 11.3%, energy efficiency by 7.4% and reduces the number of memory accesses by 10.7% at a cost of less than 0.3% additional die area.

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KW - Embedded systems

KW - Machine Learning

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Vieira J, Giacomin E, Qureshi Y, Zapater M, Tang X, Kvatinsky S et al. Accelerating inference on binary neural networks with digital rram processing. In Metzler C, Reis R, Gaillardon PE, De Micheli G, Silva-Cardenas C, editors, VLSI-SoC: New Technology Enabler - 27th IFIP/IEEE WG 10.5 International Conference on Very Large Scale Integration, VLSI-SoC 2019, Revised and Extended Selected Papers. 2020. p. 257-278. (IFIP Advances in Information and Communication Technology). doi: 10.1007/978-3-030-53273-4_12

Accelerating inference on binary neural networks with digital rram processing

Abstract

Publication series

Conference

Keywords

All Science Journal Classification (ASJC) codes

UN SDGs

Access to Document

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Cite this