TY - CHAP
T1 - abstractPIM
T2 - 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020
AU - Eliahu, Adi
AU - Ben-Hur, Rotem
AU - Ronen, Ronny
AU - Kvatinsky, Shahar
N1 - Publisher Copyright: © 2021, IFIP International Federation for Information Processing.
PY - 2021/1/1
Y1 - 2021/1/1
N2 - The von Neumann architecture, in which the memory and the computation units are separated, demands massive data traffic between the memory and the CPU. To reduce data movement, new technologies and computer architectures have been explored. The use of memristors, which are devices with both memory and computation capabilities, has been considered for different processing-in-memory (PIM) solutions, including using memristive stateful logic for a programmable digital PIM system. Nevertheless, all previous work has focused on a specific stateful logic family, and on optimizing the execution for a certain target machine. These solutions require new compiler and compilation when changing the target machine, and provide no backward compatibility with other target machines. In this chapter, we present abstractPIM, a new compilation concept and flow which enables executing any function within the memory, using different stateful logic families and different instruction set architectures (ISAs). By separating the code generation into two independent components, intermediate representation of the code using target independent ISA and then microcode generation for a specific target machine, we provide a flexible flow with backward compatibility and lay foundations for a PIM compiler. Using abstractPIM, we explore various logic technologies and ISAs and how they impact each other, and discuss the challenges associated with it, such as the increase in execution time.
AB - The von Neumann architecture, in which the memory and the computation units are separated, demands massive data traffic between the memory and the CPU. To reduce data movement, new technologies and computer architectures have been explored. The use of memristors, which are devices with both memory and computation capabilities, has been considered for different processing-in-memory (PIM) solutions, including using memristive stateful logic for a programmable digital PIM system. Nevertheless, all previous work has focused on a specific stateful logic family, and on optimizing the execution for a certain target machine. These solutions require new compiler and compilation when changing the target machine, and provide no backward compatibility with other target machines. In this chapter, we present abstractPIM, a new compilation concept and flow which enables executing any function within the memory, using different stateful logic families and different instruction set architectures (ISAs). By separating the code generation into two independent components, intermediate representation of the code using target independent ISA and then microcode generation for a specific target machine, we provide a flexible flow with backward compatibility and lay foundations for a PIM compiler. Using abstractPIM, we explore various logic technologies and ISAs and how they impact each other, and discuss the challenges associated with it, such as the increase in execution time.
KW - ISA
KW - Memristor
KW - RRAM
KW - processing-in-memory
KW - stateful logic
UR - http://www.scopus.com/inward/record.url?scp=85112687926&partnerID=8YFLogxK
U2 - https://doi.org/10.1007/978-3-030-81641-4_16
DO - https://doi.org/10.1007/978-3-030-81641-4_16
M3 - فصل
SN - 9783030816407
T3 - IFIP Advances in Information and Communication Technology
SP - 343
EP - 361
BT - VLSI-SoC
A2 - Calimera, Andrea
A2 - Gaillardon, Pierre-Emmanuel
A2 - Korgaonkar, Kunal
A2 - Kvatinsky, Shahar
A2 - Reis, Ricardo
PB - Springer Science and Business Media Deutschland GmbH
Y2 - 6 October 2020 through 9 October 2020
ER -