A Wideband CMOS Power Amplifier With 52% Peak PAE Employing Resistive Shunt Feedback for Sub-6 GHz 5G Applications

This letter presents the design and implementation of a wideband power amplifier (PA) for sub-6 GHz 5G wireless applications. The PA employs a Class-B biased cascode topology with resistive shunt&#x2013;shunt feedback for wideband response, good linearity, and simultaneous input and output matching. The design equations and stability considerations are laid out and are followed by experimental validation using both static and dynamic measurements. The chip prototype was fabricated in TSMC&#x2019;s 65 nm CMOS technology. The PA operates from a 3.3 V supply and delivers a maximum power gain of 22.5 dB with a bandwidth of 2.17 GHz between 0.33 and 2.5 GHz, a peak output power of 21.5 dBm, and 52.4% power-added efficiency (PAE) at 1 GHz with <inline-formula> <tex-math notation="LaTeX">$&gt;$</tex-math> </inline-formula>35% PAE over the operating frequency range. In the measurement of an orthogonal frequency-division multiplexing (OFDM) signal with 20 MHz modulation bandwidth and 10 dB peak-to-average power ratio (PAPR) at the average output power of 11 dBm around 1 GHz, EVM of <inline-formula> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula>39 dB was achieved using memoryless polynomial-based digital predistortion (DPD).