A RISC-V-based Research Platform for Rapid Design Cycle

Esteban Garzon; Roman Golman; Odem Harel; Tzachi Noy; Yehuda Kra; Asaf Pollock; Slava Yuzhaninov; Yonatan Shoshan; Yehuda Rudin; Yoav Weitzman; Marco Lanuzza; Adam Teman

doi:10.1109/ISCAS48785.2022.9937866

A RISC-V-based Research Platform for Rapid Design Cycle

Esteban Garzon, Roman Golman, Odem Harel, Tzachi Noy, Yehuda Kra, Asaf Pollock, Slava Yuzhaninov, Yonatan Shoshan, Yehuda Rudin, Yoav Weitzman, Marco Lanuzza, Adam Teman

Bar-Ilan University - The Alexander Kofkin Faculty of Engineering

Bar-Ilan University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This work proposes a novel platform for bringing a project from the concept to the tapeout stage in a short amount of time. An open-source and extendable RISC-V architecture is exploited to build a small area footprint core. This leads the research platform to be flexible in terms of design integration, while also allowing fast design cycles of research chips.

Original language	American English
Title of host publication	IEEE International Symposium on Circuits and Systems, ISCAS 2022
Pages	2614-2615
Number of pages	2
ISBN (Electronic)	9781665484855
DOIs	https://doi.org/10.1109/ISCAS48785.2022.9937866
State	Published - 1 Jan 2022
Event	2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022 - Austin, United States Duration: 27 May 2022 → 1 Jun 2022

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2022-May

Conference

Conference	2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022
Country/Territory	United States
City	Austin
Period	27/05/22 → 1/06/22

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS48785.2022.9937866

Cite this

Garzon, E., Golman, R., Harel, O., Noy, T., Kra, Y., Pollock, A., Yuzhaninov, S., Shoshan, Y., Rudin, Y., Weitzman, Y., Lanuzza, M., & Teman, A. (2022). A RISC-V-based Research Platform for Rapid Design Cycle. In IEEE International Symposium on Circuits and Systems, ISCAS 2022 (pp. 2614-2615). (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2022-May). https://doi.org/10.1109/ISCAS48785.2022.9937866

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title = "A RISC-V-based Research Platform for Rapid Design Cycle",

abstract = "This work proposes a novel platform for bringing a project from the concept to the tapeout stage in a short amount of time. An open-source and extendable RISC-V architecture is exploited to build a small area footprint core. This leads the research platform to be flexible in terms of design integration, while also allowing fast design cycles of research chips.",

author = "Esteban Garzon and Roman Golman and Odem Harel and Tzachi Noy and Yehuda Kra and Asaf Pollock and Slava Yuzhaninov and Yonatan Shoshan and Yehuda Rudin and Yoav Weitzman and Marco Lanuzza and Adam Teman",

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doi = "10.1109/ISCAS48785.2022.9937866",

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Garzon, E, Golman, R, Harel, O, Noy, T, Kra, Y, Pollock, A, Yuzhaninov, S, Shoshan, Y, Rudin, Y, Weitzman, Y, Lanuzza, M & Teman, A 2022, A RISC-V-based Research Platform for Rapid Design Cycle. in IEEE International Symposium on Circuits and Systems, ISCAS 2022. Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2022-May, pp. 2614-2615, 2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022, Austin, United States, 27/05/22. https://doi.org/10.1109/ISCAS48785.2022.9937866

A RISC-V-based Research Platform for Rapid Design Cycle. / Garzon, Esteban; Golman, Roman; Harel, Odem et al.
IEEE International Symposium on Circuits and Systems, ISCAS 2022. 2022. p. 2614-2615 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2022-May).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Kra, Yehuda

AU - Pollock, Asaf

AU - Yuzhaninov, Slava

AU - Shoshan, Yonatan

AU - Rudin, Yehuda

AU - Weitzman, Yoav

AU - Lanuzza, Marco

AU - Teman, Adam

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N2 - This work proposes a novel platform for bringing a project from the concept to the tapeout stage in a short amount of time. An open-source and extendable RISC-V architecture is exploited to build a small area footprint core. This leads the research platform to be flexible in terms of design integration, while also allowing fast design cycles of research chips.

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M3 - Conference contribution

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SP - 2614

EP - 2615

BT - IEEE International Symposium on Circuits and Systems, ISCAS 2022

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A RISC-V-based Research Platform for Rapid Design Cycle

Abstract

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All Science Journal Classification (ASJC) codes

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