A low-power correlator for wakeup receivers with algorithm pruning through early termination

Reza Ghanaatian; Paul N. Whatmough; Jeremy Constantin; Adam Teman; Andreas Burg

doi:10.1109/ISCAS.2016.7539142

A low-power correlator for wakeup receivers with algorithm pruning through early termination

Reza Ghanaatian, Paul N. Whatmough, Jeremy Constantin, Adam Teman, Andreas Burg

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

A low-complexity, low-power digital correlator for wakeup receivers is presented. With the proposed algorithm, unnecessary computational cycles are dynamically pruned from the correlation using an early threshold check. For the algorithm, we provide a rigorous mathematical analysis for the associated complexity/performance trade-offs. Furthermore, a low overhead hardware architecture with early-termination capability is developed and implemented in a 0.18μm CMOS technology. The post layout power analysis shows that the presented architecture can reduce power by up to 32% when compared to the conventional architecture with negligible degradation in detection probability and without degradation in false-alarm probability.

Original language	American English
Title of host publication	ISCAS 2016 - IEEE International Symposium on Circuits and Systems
Pages	2667-2670
Number of pages	4
ISBN (Electronic)	9781479953400
DOIs	https://doi.org/10.1109/ISCAS.2016.7539142
State	Published - 29 Jul 2016
Externally published	Yes
Event	2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 - Montreal, Canada Duration: 22 May 2016 → 25 May 2016

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2016-July

Conference

Conference	2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016
Country/Territory	Canada
City	Montreal
Period	22/05/16 → 25/05/16

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2016.7539142

Cite this

Ghanaatian, R., Whatmough, P. N., Constantin, J., Teman, A., & Burg, A. (2016). A low-power correlator for wakeup receivers with algorithm pruning through early termination. In ISCAS 2016 - IEEE International Symposium on Circuits and Systems (pp. 2667-2670). Article 7539142 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2016-July). https://doi.org/10.1109/ISCAS.2016.7539142

@inproceedings{00ac990388ca4288a1bc1a10cb98a2b6,

title = "A low-power correlator for wakeup receivers with algorithm pruning through early termination",

abstract = "A low-complexity, low-power digital correlator for wakeup receivers is presented. With the proposed algorithm, unnecessary computational cycles are dynamically pruned from the correlation using an early threshold check. For the algorithm, we provide a rigorous mathematical analysis for the associated complexity/performance trade-offs. Furthermore, a low overhead hardware architecture with early-termination capability is developed and implemented in a 0.18μm CMOS technology. The post layout power analysis shows that the presented architecture can reduce power by up to 32% when compared to the conventional architecture with negligible degradation in detection probability and without degradation in false-alarm probability.",

author = "Reza Ghanaatian and Whatmough, {Paul N.} and Jeremy Constantin and Adam Teman and Andreas Burg",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 ; Conference date: 22-05-2016 Through 25-05-2016",

year = "2016",

month = jul,

day = "29",

doi = "10.1109/ISCAS.2016.7539142",

language = "American English",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

pages = "2667--2670",

booktitle = "ISCAS 2016 - IEEE International Symposium on Circuits and Systems",

}

Ghanaatian, R, Whatmough, PN, Constantin, J, Teman, A & Burg, A 2016, A low-power correlator for wakeup receivers with algorithm pruning through early termination. in ISCAS 2016 - IEEE International Symposium on Circuits and Systems., 7539142, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2016-July, pp. 2667-2670, 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montreal, Canada, 22/05/16. https://doi.org/10.1109/ISCAS.2016.7539142

A low-power correlator for wakeup receivers with algorithm pruning through early termination. / Ghanaatian, Reza; Whatmough, Paul N.; Constantin, Jeremy et al.
ISCAS 2016 - IEEE International Symposium on Circuits and Systems. 2016. p. 2667-2670 7539142 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2016-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A low-power correlator for wakeup receivers with algorithm pruning through early termination

AU - Ghanaatian, Reza

AU - Whatmough, Paul N.

AU - Constantin, Jeremy

AU - Teman, Adam

AU - Burg, Andreas

PY - 2016/7/29

Y1 - 2016/7/29

N2 - A low-complexity, low-power digital correlator for wakeup receivers is presented. With the proposed algorithm, unnecessary computational cycles are dynamically pruned from the correlation using an early threshold check. For the algorithm, we provide a rigorous mathematical analysis for the associated complexity/performance trade-offs. Furthermore, a low overhead hardware architecture with early-termination capability is developed and implemented in a 0.18μm CMOS technology. The post layout power analysis shows that the presented architecture can reduce power by up to 32% when compared to the conventional architecture with negligible degradation in detection probability and without degradation in false-alarm probability.

AB - A low-complexity, low-power digital correlator for wakeup receivers is presented. With the proposed algorithm, unnecessary computational cycles are dynamically pruned from the correlation using an early threshold check. For the algorithm, we provide a rigorous mathematical analysis for the associated complexity/performance trade-offs. Furthermore, a low overhead hardware architecture with early-termination capability is developed and implemented in a 0.18μm CMOS technology. The post layout power analysis shows that the presented architecture can reduce power by up to 32% when compared to the conventional architecture with negligible degradation in detection probability and without degradation in false-alarm probability.

UR - http://www.scopus.com/inward/record.url?scp=84983397812&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2016.7539142

DO - 10.1109/ISCAS.2016.7539142

M3 - Conference contribution

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

SP - 2667

EP - 2670

BT - ISCAS 2016 - IEEE International Symposium on Circuits and Systems

T2 - 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016

Y2 - 22 May 2016 through 25 May 2016

ER -

A low-power correlator for wakeup receivers with algorithm pruning through early termination

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