A Low Power Consumption 65-nm CMOS True Time Delay N-path Circuit Achieving 2 ps Delay Resolution

Keyphrases

• Low Power Consumption 100%
• 65nm CMOS 100%
• True Time Delay 100%
• Delayed Resolution 100%
• N-path 100%
• Time Delay 50%
• Delay Variation 50%
• Mathematical Model 25%
• Small Area 25%
• Time-variant 25%
• Power Consumption 25%
• Undersampling 25%
• CMOS chip 25%
• Small Power 25%
• Relative Delay 25%
• Maximum Delay 25%
• Chip Implementation 25%
• Delay Cell 25%
• Path Topology 25%

Engineering

• Delay Time 100%
• Low Power Consumption 100%
• Periodic Time 16%
• Mathematical Model 16%
• Electric Power Utilization 16%
• Relative Delay 16%