A Low Power Consumption 65-nm CMOS True Time Delay N-path Circuit Achieving 2 ps Delay Resolution

Erez Zolkov; Roy Weiss; Asher Madjar; Emanuel Cohen

doi:https://doi.org/10.1109/EuMIC48047.2021.00061

A Low Power Consumption 65-nm CMOS True Time Delay N-path Circuit Achieving 2 ps Delay Resolution

Erez Zolkov, Roy Weiss, Asher Madjar, Emanuel Cohen

Technion - Israel Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Integrated true time delay cells are usually large in size, and have high relative delay variation. Here, the true time delay N-path topology is explored, where the signal is under-sampled with a number of parallel S/H circuits, and reconstructed and summed after a given time delay. The proposed circuit provides minimum resolution in time delay, while requiring relatively small area and power. The effect of the true time delay is analyzed with a linear periodic time-variant mathematical model, and is verified through measurements. Measurements of 65-nm CMOS chip implementation show up to 2 ns delay for bandwidth of 400 MHz, with maximum delay variation over frequency of 14 ps, delay resolution of 2 ps and power consumption of 9.6 mW.

Original language	English
Title of host publication	EuMIC 2020 - 2020 15th European Microwave Integrated Circuits Conference
Pages	197-200
Number of pages	4
ISBN (Electronic)	9782874870606
DOIs	https://doi.org/10.1109/EuMIC48047.2021.00061
State	Published - 10 Jan 2021
Event	15th European Microwave Integrated Circuits Conference, EuMIC 2020 - Utrecht, Netherlands Duration: 11 Jan 2021 → 12 Jan 2021

Publication series

Name	EuMIC 2020 - 2020 15th European Microwave Integrated Circuits Conference

Conference

Conference	15th European Microwave Integrated Circuits Conference, EuMIC 2020
Country/Territory	Netherlands
City	Utrecht
Period	11/01/21 → 12/01/21

Keywords

CMOS
LPTV circuits
True time delay

All Science Journal Classification (ASJC) codes

Computer Networks and Communications
Hardware and Architecture
Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials
Instrumentation

Access to Document

https://doi.org/10.1109/EuMIC48047.2021.00061

Cite this

Zolkov, E., Weiss, R., Madjar, A., & Cohen, E. (2021). A Low Power Consumption 65-nm CMOS True Time Delay N-path Circuit Achieving 2 ps Delay Resolution. In EuMIC 2020 - 2020 15th European Microwave Integrated Circuits Conference (pp. 197-200). Article 9337475 (EuMIC 2020 - 2020 15th European Microwave Integrated Circuits Conference). https://doi.org/10.1109/EuMIC48047.2021.00061

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title = "A Low Power Consumption 65-nm CMOS True Time Delay N-path Circuit Achieving 2 ps Delay Resolution",

abstract = "Integrated true time delay cells are usually large in size, and have high relative delay variation. Here, the true time delay N-path topology is explored, where the signal is under-sampled with a number of parallel S/H circuits, and reconstructed and summed after a given time delay. The proposed circuit provides minimum resolution in time delay, while requiring relatively small area and power. The effect of the true time delay is analyzed with a linear periodic time-variant mathematical model, and is verified through measurements. Measurements of 65-nm CMOS chip implementation show up to 2 ns delay for bandwidth of 400 MHz, with maximum delay variation over frequency of 14 ps, delay resolution of 2 ps and power consumption of 9.6 mW.",

keywords = "CMOS, LPTV circuits, True time delay",

author = "Erez Zolkov and Roy Weiss and Asher Madjar and Emanuel Cohen",

note = "Publisher Copyright: {\textcopyright} 2021 EuMA.; 15th European Microwave Integrated Circuits Conference, EuMIC 2020 ; Conference date: 11-01-2021 Through 12-01-2021",

year = "2021",

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doi = "https://doi.org/10.1109/EuMIC48047.2021.00061",

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Zolkov, E, Weiss, R, Madjar, A & Cohen, E 2021, A Low Power Consumption 65-nm CMOS True Time Delay N-path Circuit Achieving 2 ps Delay Resolution. in EuMIC 2020 - 2020 15th European Microwave Integrated Circuits Conference., 9337475, EuMIC 2020 - 2020 15th European Microwave Integrated Circuits Conference, pp. 197-200, 15th European Microwave Integrated Circuits Conference, EuMIC 2020, Utrecht, Netherlands, 11/01/21. https://doi.org/10.1109/EuMIC48047.2021.00061

A Low Power Consumption 65-nm CMOS True Time Delay N-path Circuit Achieving 2 ps Delay Resolution. / Zolkov, Erez; Weiss, Roy; Madjar, Asher et al.
EuMIC 2020 - 2020 15th European Microwave Integrated Circuits Conference. 2021. p. 197-200 9337475 (EuMIC 2020 - 2020 15th European Microwave Integrated Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A Low Power Consumption 65-nm CMOS True Time Delay N-path Circuit Achieving 2 ps Delay Resolution

AU - Zolkov, Erez

AU - Weiss, Roy

AU - Madjar, Asher

AU - Cohen, Emanuel

PY - 2021/1/10

Y1 - 2021/1/10

N2 - Integrated true time delay cells are usually large in size, and have high relative delay variation. Here, the true time delay N-path topology is explored, where the signal is under-sampled with a number of parallel S/H circuits, and reconstructed and summed after a given time delay. The proposed circuit provides minimum resolution in time delay, while requiring relatively small area and power. The effect of the true time delay is analyzed with a linear periodic time-variant mathematical model, and is verified through measurements. Measurements of 65-nm CMOS chip implementation show up to 2 ns delay for bandwidth of 400 MHz, with maximum delay variation over frequency of 14 ps, delay resolution of 2 ps and power consumption of 9.6 mW.

AB - Integrated true time delay cells are usually large in size, and have high relative delay variation. Here, the true time delay N-path topology is explored, where the signal is under-sampled with a number of parallel S/H circuits, and reconstructed and summed after a given time delay. The proposed circuit provides minimum resolution in time delay, while requiring relatively small area and power. The effect of the true time delay is analyzed with a linear periodic time-variant mathematical model, and is verified through measurements. Measurements of 65-nm CMOS chip implementation show up to 2 ns delay for bandwidth of 400 MHz, with maximum delay variation over frequency of 14 ps, delay resolution of 2 ps and power consumption of 9.6 mW.

KW - CMOS

KW - LPTV circuits

KW - True time delay

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M3 - منشور من مؤتمر

T3 - EuMIC 2020 - 2020 15th European Microwave Integrated Circuits Conference

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T2 - 15th European Microwave Integrated Circuits Conference, EuMIC 2020

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A Low Power Consumption 65-nm CMOS True Time Delay N-path Circuit Achieving 2 ps Delay Resolution

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