Abstract
Building on the Half-Wave Cockcroft-Walton voltage multiplier, a topology is proposed that consists of several voltage multiplying sections fed separately at their inputs and whose output voltages are summated across the load. The proposed topology can attain over m times higher voltage gain (m being the splitting level). The theory is supported by simulations and experiments. For instance, in a simple experiment, the load voltage has increased from 2.8 kV to 6.6 kV due to splitting the circuit into 3 sections (m=3).
| Original language | English |
|---|---|
| Pages | 3272-3275 |
| Number of pages | 4 |
| DOIs | |
| State | Published - 8 May 2015 |
| Event | 30th Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2015 - Charlotte, United States Duration: 15 Mar 2015 → 19 Mar 2015 |
Conference
| Conference | 30th Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2015 |
|---|---|
| Country/Territory | United States |
| City | Charlotte |
| Period | 15/03/15 → 19/03/15 |
Keywords
- Half-Wave Cockcroft-Walton
- High Voltage
- Voltage multiplier
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering