A fully integrated multi-CPU, processor graphics, and memory controller 32-nm processor

Marcelo Yuffe; Moty Mehalel; Ernest Knoll; Joseph Shor; Tsvika Kurts; Eran Altshuler; Eyal Fayneh; Kosta Luria; Michael Zelikson

doi:10.1109/jssc.2011.2167814

A fully integrated multi-CPU, processor graphics, and memory controller 32-nm processor

Marcelo Yuffe, Moty Mehalel, Ernest Knoll, Joseph Shor, Tsvika Kurts, Eran Altshuler, Eyal Fayneh, Kosta Luria, Michael Zelikson

Research output: Contribution to journal › Article › peer-review

Abstract

This paper describes the second-generation Intel Core processor, a 32-nm monolithic die integrating four IA cores, a processor graphics, and a memory controller. Special attention is given to the circuit design challenges associated with this kind of integration. The paper describes the chip floor plan, the power delivery network, energy conservation techniques, the clock generation and distribution, the on-die thermal sensors, and a novel debug port.

Original language	English
Article number	6044730
Pages (from-to)	194-205
Number of pages	12
Journal	IEEE Journal of Solid-State Circuits
Volume	47
Issue number	1
DOIs	https://doi.org/10.1109/jssc.2011.2167814
State	Published - Jan 2012
Externally published	Yes

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

Clocking
Intel second-generation core
low Vccmin
modularity
power gates
thermal sensors

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/jssc.2011.2167814

Cite this

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title = "A fully integrated multi-CPU, processor graphics, and memory controller 32-nm processor",

abstract = "This paper describes the second-generation Intel Core processor, a 32-nm monolithic die integrating four IA cores, a processor graphics, and a memory controller. Special attention is given to the circuit design challenges associated with this kind of integration. The paper describes the chip floor plan, the power delivery network, energy conservation techniques, the clock generation and distribution, the on-die thermal sensors, and a novel debug port.",

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author = "Marcelo Yuffe and Moty Mehalel and Ernest Knoll and Joseph Shor and Tsvika Kurts and Eran Altshuler and Eyal Fayneh and Kosta Luria and Michael Zelikson",

year = "2012",

month = jan,

doi = "10.1109/jssc.2011.2167814",

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AU - Mehalel, Moty

AU - Knoll, Ernest

AU - Shor, Joseph

AU - Kurts, Tsvika

AU - Altshuler, Eran

AU - Fayneh, Eyal

AU - Luria, Kosta

AU - Zelikson, Michael

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AB - This paper describes the second-generation Intel Core processor, a 32-nm monolithic die integrating four IA cores, a processor graphics, and a memory controller. Special attention is given to the circuit design challenges associated with this kind of integration. The paper describes the chip floor plan, the power delivery network, energy conservation techniques, the clock generation and distribution, the on-die thermal sensors, and a novel debug port.

KW - Clocking

KW - Intel second-generation core

KW - low Vccmin

KW - modularity

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KW - thermal sensors

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M3 - مقالة

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JO - IEEE Journal of Solid-State Circuits

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ER -

A fully integrated multi-CPU, processor graphics, and memory controller 32-nm processor

Abstract

UN SDGs

Keywords

All Science Journal Classification (ASJC) codes

Access to Document

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