A Distributed Cascode Power Amplifier with an Integrated Analog SIC Filter for Full-Duplex Wireless Operation in 65 nm CMOS

Itamar Melamed; Nimrod Ginzberg; Omer Malka; Emanuel Cohen

doi:10.1109/RFIC54547.2023.10186122

A Distributed Cascode Power Amplifier with an Integrated Analog SIC Filter for Full-Duplex Wireless Operation in 65 nm CMOS

Itamar Melamed, Nimrod Ginzberg, Omer Malka, Emanuel Cohen

Technion - Israel Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this work, we propose a fully integrated transmitter front-end based on a balanced distributed cascode power amplifier and a passive second-order reconfigurable reflective self-interference cancellation (SIC) filter for full-duplex wireless applications. The balanced topology provides inherent passive transmit-receive (TX-RX) isolation complemented by the passive SIC filter, which accounts for the signal, noise, and nonlinearity components of the direct TX-RX leakages and the reflections from a commercial Wi-Fi antenna. A front-end chip prototype fabricated in TSMC's 65 nm CMOS process operating between 5-6 GHz and occupying the area of 1.2 mm2achieves 19.5 dBm Psat with 31% peak PAE, 17 dBm OP1dB, and 8-10 dB RX noise figure, along with 40 dB of TX-RX isolation and -30 dB TX EVM at 10 dB power backoff using a 20 MHz Wi-Fi OFDM signal without DPD.

Original language	English
Title of host publication	2023 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2023
Editors	Jennifer Kitchen, Steven Turner
Pages	221-224
Number of pages	4
ISBN (Electronic)	9798350321227
DOIs	https://doi.org/10.1109/RFIC54547.2023.10186122
State	Published - 2023
Event	2023 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2023 - San Diego, United States Duration: 11 Jun 2023 → 13 Jun 2023

Publication series

Name	Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
Volume	2023-June

Conference

Conference	2023 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2023
Country/Territory	United States
City	San Diego
Period	11/06/23 → 13/06/23

Keywords

Electrical-Balanced Duplexer (EBD)
Full-duplex
Power Amplifier
self-interference cancellation (SIC)

All Science Journal Classification (ASJC) codes

General Engineering

Access to Document

10.1109/RFIC54547.2023.10186122

Cite this

Melamed, I., Ginzberg, N., Malka, O., & Cohen, E. (2023). A Distributed Cascode Power Amplifier with an Integrated Analog SIC Filter for Full-Duplex Wireless Operation in 65 nm CMOS. In J. Kitchen, & S. Turner (Eds.), 2023 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2023 (pp. 221-224). (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium; Vol. 2023-June). https://doi.org/10.1109/RFIC54547.2023.10186122

Melamed, Itamar ; Ginzberg, Nimrod ; Malka, Omer et al. / A Distributed Cascode Power Amplifier with an Integrated Analog SIC Filter for Full-Duplex Wireless Operation in 65 nm CMOS. 2023 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2023. editor / Jennifer Kitchen ; Steven Turner. 2023. pp. 221-224 (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium).

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title = "A Distributed Cascode Power Amplifier with an Integrated Analog SIC Filter for Full-Duplex Wireless Operation in 65 nm CMOS",

abstract = "In this work, we propose a fully integrated transmitter front-end based on a balanced distributed cascode power amplifier and a passive second-order reconfigurable reflective self-interference cancellation (SIC) filter for full-duplex wireless applications. The balanced topology provides inherent passive transmit-receive (TX-RX) isolation complemented by the passive SIC filter, which accounts for the signal, noise, and nonlinearity components of the direct TX-RX leakages and the reflections from a commercial Wi-Fi antenna. A front-end chip prototype fabricated in TSMC's 65 nm CMOS process operating between 5-6 GHz and occupying the area of 1.2 mm2achieves 19.5 dBm Psat with 31% peak PAE, 17 dBm OP1dB, and 8-10 dB RX noise figure, along with 40 dB of TX-RX isolation and -30 dB TX EVM at 10 dB power backoff using a 20 MHz Wi-Fi OFDM signal without DPD.",

keywords = "Electrical-Balanced Duplexer (EBD), Full-duplex, Power Amplifier, self-interference cancellation (SIC)",

author = "Itamar Melamed and Nimrod Ginzberg and Omer Malka and Emanuel Cohen",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 2023 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2023 ; Conference date: 11-06-2023 Through 13-06-2023",

year = "2023",

doi = "10.1109/RFIC54547.2023.10186122",

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Melamed, I, Ginzberg, N, Malka, O & Cohen, E 2023, A Distributed Cascode Power Amplifier with an Integrated Analog SIC Filter for Full-Duplex Wireless Operation in 65 nm CMOS. in J Kitchen & S Turner (eds), 2023 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2023. Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium, vol. 2023-June, pp. 221-224, 2023 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2023, San Diego, United States, 11/06/23. https://doi.org/10.1109/RFIC54547.2023.10186122

A Distributed Cascode Power Amplifier with an Integrated Analog SIC Filter for Full-Duplex Wireless Operation in 65 nm CMOS. / Melamed, Itamar; Ginzberg, Nimrod; Malka, Omer et al.
2023 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2023. ed. / Jennifer Kitchen; Steven Turner. 2023. p. 221-224 (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium; Vol. 2023-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - In this work, we propose a fully integrated transmitter front-end based on a balanced distributed cascode power amplifier and a passive second-order reconfigurable reflective self-interference cancellation (SIC) filter for full-duplex wireless applications. The balanced topology provides inherent passive transmit-receive (TX-RX) isolation complemented by the passive SIC filter, which accounts for the signal, noise, and nonlinearity components of the direct TX-RX leakages and the reflections from a commercial Wi-Fi antenna. A front-end chip prototype fabricated in TSMC's 65 nm CMOS process operating between 5-6 GHz and occupying the area of 1.2 mm2achieves 19.5 dBm Psat with 31% peak PAE, 17 dBm OP1dB, and 8-10 dB RX noise figure, along with 40 dB of TX-RX isolation and -30 dB TX EVM at 10 dB power backoff using a 20 MHz Wi-Fi OFDM signal without DPD.

AB - In this work, we propose a fully integrated transmitter front-end based on a balanced distributed cascode power amplifier and a passive second-order reconfigurable reflective self-interference cancellation (SIC) filter for full-duplex wireless applications. The balanced topology provides inherent passive transmit-receive (TX-RX) isolation complemented by the passive SIC filter, which accounts for the signal, noise, and nonlinearity components of the direct TX-RX leakages and the reflections from a commercial Wi-Fi antenna. A front-end chip prototype fabricated in TSMC's 65 nm CMOS process operating between 5-6 GHz and occupying the area of 1.2 mm2achieves 19.5 dBm Psat with 31% peak PAE, 17 dBm OP1dB, and 8-10 dB RX noise figure, along with 40 dB of TX-RX isolation and -30 dB TX EVM at 10 dB power backoff using a 20 MHz Wi-Fi OFDM signal without DPD.

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ER -

Melamed I, Ginzberg N, Malka O, Cohen E. A Distributed Cascode Power Amplifier with an Integrated Analog SIC Filter for Full-Duplex Wireless Operation in 65 nm CMOS. In Kitchen J, Turner S, editors, 2023 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2023. 2023. p. 221-224. (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium). doi: 10.1109/RFIC54547.2023.10186122

A Distributed Cascode Power Amplifier with an Integrated Analog SIC Filter for Full-Duplex Wireless Operation in 65 nm CMOS

Abstract

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Keywords

All Science Journal Classification (ASJC) codes

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