@inproceedings{d9444f4545b645e4b3e617b8874caa82,
title = "A 5-Transistor Ternary Gain-Cell eDRAM with Parallel Sensing",
abstract = "Embedded memories dominate area, power, and cost of modern VLSI system-on-chips. While static random access memory (SRAM) is the dominant technology for implementing these memories, Gain-cell embedded DRAM (GC-eDRAM) has been suggested as a possible alternative in recent years. This technology has been shown to provide low-power, logic compatible storage in a reduced silicon footprint, as compared to conventional SRAM. In this paper we suggest a novel GC-eDRAM topology that is capable of storing three voltage levels within a single cell, further improving upon the area and energy-per-bit of the storage solution. The proposed ternary gain-cell is designed in a standard CMOS 65 nm technology node using a low overhead 1/2 VDD write driver for ternary writes and a parallel sensing scheme composed of skewed sense inverters for ternary readout. The proposed approach provides over 3× reduction in static power with a 48% reduction of area-per-bit in comparison with a conventional SRAM cell in the same technology.",
author = "Or Maltabashi and Hanan Marinberg and Robert Giterman and Adam Teman",
note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 ; Conference date: 27-05-2018 Through 30-05-2018",
year = "2018",
month = apr,
day = "26",
doi = "https://doi.org/10.1109/ISCAS.2018.8351360",
language = "الإنجليزيّة",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings",
address = "الولايات المتّحدة",
}