@inproceedings{3c3a90acc2174c7aa5c929a91b4b24bf,
title = "A 30 GHz 4.2 mW 105 fsec Jitter Sub-Sampling PLL with 1° Phase Shift Resolution in 65 nm CMOS",
abstract = "This paper presents a low-power and a low-noise 30 GHz, sub-sampling phase-locked loop (SSPLL) with a 1° phase shift resolution for millimeter-wave phased arrays. Phase shifting is integrated into the PLL for low power consumption and operates at low frequencies. Using a two-point phase-shifting, the SSPLL achieves a high-resolution phase-shift with relaxed circuit complexity. Inductive coupling between the VCO and the feedback loop eliminates the VCO butter with minimal loading. Implemented in a standard 65 nm bulk-CMOS process, the VCO consumes 2.9 mW with a tuning range between 29. 3-31.2GHz. It dissipates 4.2 mW from a 1. 2V supply with a jitter of 105 fsec that achieves phase shift resolution of 1°, reference spur of -60dBc, and a PLL FoM of -253dB.",
keywords = "5G, CMOS, digital-to-time converter, low-noise, low-power, mm-wave phased-array, sub-sampling PLL (SSPLL)",
author = "Itamar Melamed and Emanuel Cohen",
note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 22nd IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2022 ; Conference date: 16-01-2022 Through 19-01-2022",
year = "2022",
doi = "10.1109/SiRF53094.2022.9720065",
language = "الإنجليزيّة",
series = "2022 IEEE 22nd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2022",
pages = "45--48",
booktitle = "2022 IEEE 22nd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2022",
}