@inproceedings{34b90540711e454abef8ab34d3d2a400,
title = "A 11.5pW/bit 400mV 5T gain-cell eDRAM for ULP applications in 28nm FD-SOI",
abstract = "The silicon area of ultra-low power (ULP) applications is often dominated by embedded memories, which are the main consumers of both the static and dynamic power in these applications [1]. Supply voltage scaling down to the sub-threshold region is widely used to significantly reduce both the static and dynamic power dissipation of ULP applications [2]. However, embedded memories, typically implemented with SRAM, have been the limiting factor for aggressive voltage scaling, since the conventional 6-transistor (6T) SRAM bitcell becomes unreliable at near-threshold operating voltages [3-6].",
author = "Robert Giterman and Adam Teman and Alexander Fish",
note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017 ; Conference date: 16-10-2017 Through 18-10-2017",
year = "2017",
month = jul,
day = "2",
doi = "10.1109/s3s.2017.8308757",
language = "الإنجليزيّة",
series = "2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1--3",
booktitle = "2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017",
address = "الولايات المتّحدة",
}