A 0.8-V, 1.54-pJ/940-MHz Dual-Mode Logic-Based 16×16-b Booth Multiplier in 16-nm FinFET

Netanel Shavit; Inbal Stanger; Ramiro Taco; Marco Lanuzza; Alexander Fish

doi:10.1109/lssc.2020.3011636

A 0.8-V, 1.54-pJ/940-MHz Dual-Mode Logic-Based 16×16-b Booth Multiplier in 16-nm FinFET

Netanel Shavit, Inbal Stanger, Ramiro Taco, Marco Lanuzza, Alexander Fish

Bar-Ilan University - The Alexander Kofkin Faculty of Engineering

Bar-Ilan University

Research output: Contribution to journal › Article › peer-review

Abstract

The dual-mode logic (DML) defines runtime adapted digital architectures that switch to either improved performance or lower energy consumption as a function of the actual computational workload. This flexibility is demonstrated for the first time by silicon measurements on a 16\times 16 -b Booth multiplier fabricated as a part of an ultralow-power digital signal processing (DSP) architecture for 16-nm FinFET technology. When running in the full-speed mode, the DML multiplier can achieve a performance boost of 19.5% as compared to the equivalent standard CMOS design. The same circuit saves precious energy (-27%, on average) when the energy-efficient mode is enabled, while occupying 13% less silicon area.

Original language	English
Article number	9146537
Pages (from-to)	314-317
Number of pages	4
Journal	IEEE Solid-State Circuits Letters
Volume	3
DOIs	https://doi.org/10.1109/lssc.2020.3011636
State	Published - 1 Jan 2020

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

Adaptive design
digital signal processing (DSP)
dual-mode logic (DML)

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/lssc.2020.3011636

Cite this

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title = "A 0.8-V, 1.54-pJ/940-MHz Dual-Mode Logic-Based 16×16-b Booth Multiplier in 16-nm FinFET",

abstract = "The dual-mode logic (DML) defines runtime adapted digital architectures that switch to either improved performance or lower energy consumption as a function of the actual computational workload. This flexibility is demonstrated for the first time by silicon measurements on a 16\textbackslash{}times 16 -b Booth multiplier fabricated as a part of an ultralow-power digital signal processing (DSP) architecture for 16-nm FinFET technology. When running in the full-speed mode, the DML multiplier can achieve a performance boost of 19.5\% as compared to the equivalent standard CMOS design. The same circuit saves precious energy (-27\%, on average) when the energy-efficient mode is enabled, while occupying 13\% less silicon area.",

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author = "Netanel Shavit and Inbal Stanger and Ramiro Taco and Marco Lanuzza and Alexander Fish",

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AU - Lanuzza, Marco

AU - Fish, Alexander

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A 0.8-V, 1.54-pJ/940-MHz Dual-Mode Logic-Based 16×16-b Booth Multiplier in 16-nm FinFET

Abstract

UN SDGs

Keywords

All Science Journal Classification (ASJC) codes

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