A 0.2-3-GHz N-Path True Time Delay Circuit Achieving <1% Delay Variation over Frequency

Erez Zolkov, Emanuel Cohen

Research output: Contribution to journalArticlepeer-review


N -path true time delay (TTD) circuits are highly attractive due to their high delay-bandwidth product, wideband response, scalability, and small size. However, in its standalone form, it cannot provide wideband input and output matching. To overcome these issues, we present a modified circuit of the N -path TTD that includes an input low-noise amplifier (LNA) and an output buffer. The N -path TTD response and its nonideal properties are analyzed further. A design guide is suggested, and an alternative isolated sampling switch is proposed. We present a 65-nm CMOS dedicated implementation, where the fine-tuning of the TTD is achieved by introducing two synchronized external local oscillator (LO) signals, with a relative shift between them. The core chip size is 0.32 \,× \,0.575 mm2, and its power consumption is 30 mW for all delay states. In our implementation, we achieve a delay range of 1 ns for bandwidth (BW) of 0.2-3 GHz with a gain standard deviation (STD) of less than 0.14 dB between delay states and a relative delay STD of less than 10 ps (1%) over frequency.

Original languageEnglish
Pages (from-to)3224-3233
Number of pages10
JournalIEEE Transactions on Microwave Theory and Techniques
Issue number6
StatePublished - 1 Jun 2022


  • CMOS
  • Clocks
  • Delay effects
  • Delays
  • Impedance matching
  • N-path
  • Switches
  • Voltage
  • Wideband
  • phased array
  • true time delay (TTD).

All Science Journal Classification (ASJC) codes

  • Radiation
  • Condensed Matter Physics
  • Electrical and Electronic Engineering


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