TY - GEN
T1 - Dual-use low-drop-out regulator/power gate with linear and on-off conduction modes for microprocessor on-die supply voltages in 14nm
AU - Luria, Kosta
AU - Shor, Joseph
AU - Zelikson, Michael
AU - Lyakhov, Alex
N1 - Publisher Copyright: © 2015 IEEE.
PY - 2015/3/17
Y1 - 2015/3/17
N2 - In recent generations of microprocessors, there has been an increase in the number and types of processors integrated on the same die. For example, in [1] several IA (Intel architecture) cores have been integrated on-chip with a graphics processor. Multi-core trends are expected to increase in future generations with different cores and units requiring varying supply voltages. As platform footprints are also required to decrease, this causes a unique challenge for voltage regulation. In [2], an on-die switching fully integrated voltage regulator (FIVR) was demonstrated, which presents a very good solution in many cases. However, the FIVR requires inductors, which may not always be available. In addition, it may be desirable to sub-divide some of the FIVR domains using power gates and/or linear voltage regulators, such as low-drop-out regulators (LDO). LDOs can be used to enable different units of the chip to operate at their optimal voltage levels, which could save power. For example, different types of cores often have significantly different minimum-Vcc levels in low-power mode. In addition, a core or graphics unit could enter a high-performance mode, where the voltage is ramped up to enable performance, while other cores are in sleep or low-power modes.
AB - In recent generations of microprocessors, there has been an increase in the number and types of processors integrated on the same die. For example, in [1] several IA (Intel architecture) cores have been integrated on-chip with a graphics processor. Multi-core trends are expected to increase in future generations with different cores and units requiring varying supply voltages. As platform footprints are also required to decrease, this causes a unique challenge for voltage regulation. In [2], an on-die switching fully integrated voltage regulator (FIVR) was demonstrated, which presents a very good solution in many cases. However, the FIVR requires inductors, which may not always be available. In addition, it may be desirable to sub-divide some of the FIVR domains using power gates and/or linear voltage regulators, such as low-drop-out regulators (LDO). LDOs can be used to enable different units of the chip to operate at their optimal voltage levels, which could save power. For example, different types of cores often have significantly different minimum-Vcc levels in low-power mode. In addition, a core or graphics unit could enter a high-performance mode, where the voltage is ramped up to enable performance, while other cores are in sleep or low-power modes.
UR - http://www.scopus.com/inward/record.url?scp=84940764589&partnerID=8YFLogxK
U2 - 10.1109/isscc.2015.7062973
DO - 10.1109/isscc.2015.7062973
M3 - منشور من مؤتمر
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 156
EP - 157
BT - 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2015 62nd IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers
Y2 - 22 February 2015 through 26 February 2015
ER -