193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing

Davide Rossi; Antonio Pullini; Igor Loi; Michael Gautschi; Frank Kagan Gurkaynak; Adam Teman; Jeremy Constantin; Andreas Burg; Ivan Miro-Panades; Edith Beign; Fabien Clermidy; Fady Abouzeid; Philippe Flatresse; Luca Benini

doi:10.1109/CoolChips.2016.7503670

193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing

Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gurkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro-Panades, Edith Beign, Fabien Clermidy, Fady Abouzeid, Philippe Flatresse, Luca Benini

Bar-Ilan University - The Alexander Kofkin Faculty of Engineering

Bar-Ilan University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Low power (mW) and high performance (GOPS) are strong requirements for compute-intensive signal processing in E-health, Internet-of-Things, and wearable applications. This work presents a building block for programmable Ultra-Low Power accelerators, namely a tightly-coupled computing cluster that supports parallel and sequential execution at high energy efficiency over a wide range of workload requirements. The cluster, implemented in 28nm UTBB FD-SOI technology, achieves peak energy efficiency in the near-threshold (NVT) operating region: 193 MOPS/mW at 162 MOPS for parallel workloads, and 90 MOPS/mW at 68 MOPS for sequential workloads at 0.46V and 0.5V, respectively. The energy efficient operating range is wide (0.32V to 1.15V), also meeting the design goal of 1 GOPS within a 10 mW power envelope (at 0.66V).

Original language	American English
Title of host publication	19th IEEE Symposium on Low-Power and High-Speed Chips, IEEE COOL Chips 2016 - Proceedings
ISBN (Electronic)	9781509013869
DOIs	https://doi.org/10.1109/CoolChips.2016.7503670
State	Published - 5 Jul 2016
Event	19th IEEE Symposium on Low-Power and High-Speed Chips, IEEE COOL Chips 2016 - Yokohama, Japan Duration: 20 Apr 2016 → 22 Apr 2016

Publication series

Name	19th IEEE Symposium on Low-Power and High-Speed Chips, IEEE COOL Chips 2016 - Proceedings

Conference

Conference	19th IEEE Symposium on Low-Power and High-Speed Chips, IEEE COOL Chips 2016
Country/Territory	Japan
City	Yokohama
Period	20/04/16 → 22/04/16

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

Body Biasing
Energy Efficiency
Parallel Processing
Power Management
UTBB FD-SOI

All Science Journal Classification (ASJC) codes

Hardware and Architecture

Access to Document

10.1109/CoolChips.2016.7503670

Cite this

Rossi, D., Pullini, A., Loi, I., Gautschi, M., Gurkaynak, F. K., Teman, A., Constantin, J., Burg, A., Miro-Panades, I., Beign, E., Clermidy, F., Abouzeid, F., Flatresse, P., & Benini, L. (2016). 193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing. In 19th IEEE Symposium on Low-Power and High-Speed Chips, IEEE COOL Chips 2016 - Proceedings Article 7503670 (19th IEEE Symposium on Low-Power and High-Speed Chips, IEEE COOL Chips 2016 - Proceedings). https://doi.org/10.1109/CoolChips.2016.7503670

Rossi, Davide ; Pullini, Antonio ; Loi, Igor et al. / 193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing. 19th IEEE Symposium on Low-Power and High-Speed Chips, IEEE COOL Chips 2016 - Proceedings. 2016. (19th IEEE Symposium on Low-Power and High-Speed Chips, IEEE COOL Chips 2016 - Proceedings).

@inproceedings{acd2fce77ca0418796a342a188b2f715,

title = "193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing",

abstract = "Low power (mW) and high performance (GOPS) are strong requirements for compute-intensive signal processing in E-health, Internet-of-Things, and wearable applications. This work presents a building block for programmable Ultra-Low Power accelerators, namely a tightly-coupled computing cluster that supports parallel and sequential execution at high energy efficiency over a wide range of workload requirements. The cluster, implemented in 28nm UTBB FD-SOI technology, achieves peak energy efficiency in the near-threshold (NVT) operating region: 193 MOPS/mW at 162 MOPS for parallel workloads, and 90 MOPS/mW at 68 MOPS for sequential workloads at 0.46V and 0.5V, respectively. The energy efficient operating range is wide (0.32V to 1.15V), also meeting the design goal of 1 GOPS within a 10 mW power envelope (at 0.66V).",

keywords = "Body Biasing, Energy Efficiency, Parallel Processing, Power Management, UTBB FD-SOI",

author = "Davide Rossi and Antonio Pullini and Igor Loi and Michael Gautschi and Gurkaynak, \{Frank Kagan\} and Adam Teman and Jeremy Constantin and Andreas Burg and Ivan Miro-Panades and Edith Beign and Fabien Clermidy and Fady Abouzeid and Philippe Flatresse and Luca Benini",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 19th IEEE Symposium on Low-Power and High-Speed Chips, IEEE COOL Chips 2016 ; Conference date: 20-04-2016 Through 22-04-2016",

year = "2016",

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doi = "10.1109/CoolChips.2016.7503670",

language = "American English",

series = "19th IEEE Symposium on Low-Power and High-Speed Chips, IEEE COOL Chips 2016 - Proceedings",

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Rossi, D, Pullini, A, Loi, I, Gautschi, M, Gurkaynak, FK, Teman, A, Constantin, J, Burg, A, Miro-Panades, I, Beign, E, Clermidy, F, Abouzeid, F, Flatresse, P & Benini, L 2016, 193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing. in 19th IEEE Symposium on Low-Power and High-Speed Chips, IEEE COOL Chips 2016 - Proceedings., 7503670, 19th IEEE Symposium on Low-Power and High-Speed Chips, IEEE COOL Chips 2016 - Proceedings, 19th IEEE Symposium on Low-Power and High-Speed Chips, IEEE COOL Chips 2016, Yokohama, Japan, 20/04/16. https://doi.org/10.1109/CoolChips.2016.7503670

193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing. / Rossi, Davide; Pullini, Antonio; Loi, Igor et al.
19th IEEE Symposium on Low-Power and High-Speed Chips, IEEE COOL Chips 2016 - Proceedings. 2016. 7503670 (19th IEEE Symposium on Low-Power and High-Speed Chips, IEEE COOL Chips 2016 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - 193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing

AU - Rossi, Davide

AU - Pullini, Antonio

AU - Loi, Igor

AU - Gautschi, Michael

AU - Gurkaynak, Frank Kagan

AU - Teman, Adam

AU - Constantin, Jeremy

AU - Burg, Andreas

AU - Miro-Panades, Ivan

AU - Beign, Edith

AU - Clermidy, Fabien

AU - Abouzeid, Fady

AU - Flatresse, Philippe

AU - Benini, Luca

PY - 2016/7/5

Y1 - 2016/7/5

N2 - Low power (mW) and high performance (GOPS) are strong requirements for compute-intensive signal processing in E-health, Internet-of-Things, and wearable applications. This work presents a building block for programmable Ultra-Low Power accelerators, namely a tightly-coupled computing cluster that supports parallel and sequential execution at high energy efficiency over a wide range of workload requirements. The cluster, implemented in 28nm UTBB FD-SOI technology, achieves peak energy efficiency in the near-threshold (NVT) operating region: 193 MOPS/mW at 162 MOPS for parallel workloads, and 90 MOPS/mW at 68 MOPS for sequential workloads at 0.46V and 0.5V, respectively. The energy efficient operating range is wide (0.32V to 1.15V), also meeting the design goal of 1 GOPS within a 10 mW power envelope (at 0.66V).

AB - Low power (mW) and high performance (GOPS) are strong requirements for compute-intensive signal processing in E-health, Internet-of-Things, and wearable applications. This work presents a building block for programmable Ultra-Low Power accelerators, namely a tightly-coupled computing cluster that supports parallel and sequential execution at high energy efficiency over a wide range of workload requirements. The cluster, implemented in 28nm UTBB FD-SOI technology, achieves peak energy efficiency in the near-threshold (NVT) operating region: 193 MOPS/mW at 162 MOPS for parallel workloads, and 90 MOPS/mW at 68 MOPS for sequential workloads at 0.46V and 0.5V, respectively. The energy efficient operating range is wide (0.32V to 1.15V), also meeting the design goal of 1 GOPS within a 10 mW power envelope (at 0.66V).

KW - Body Biasing

KW - Energy Efficiency

KW - Parallel Processing

KW - Power Management

KW - UTBB FD-SOI

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U2 - 10.1109/CoolChips.2016.7503670

DO - 10.1109/CoolChips.2016.7503670

M3 - Conference contribution

T3 - 19th IEEE Symposium on Low-Power and High-Speed Chips, IEEE COOL Chips 2016 - Proceedings

BT - 19th IEEE Symposium on Low-Power and High-Speed Chips, IEEE COOL Chips 2016 - Proceedings

T2 - 19th IEEE Symposium on Low-Power and High-Speed Chips, IEEE COOL Chips 2016

Y2 - 20 April 2016 through 22 April 2016

ER -

Rossi D, Pullini A, Loi I, Gautschi M, Gurkaynak FK, Teman A et al. 193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing. In 19th IEEE Symposium on Low-Power and High-Speed Chips, IEEE COOL Chips 2016 - Proceedings. 2016. 7503670. (19th IEEE Symposium on Low-Power and High-Speed Chips, IEEE COOL Chips 2016 - Proceedings). doi: 10.1109/CoolChips.2016.7503670

193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing

Abstract

Publication series

Conference

UN SDGs

Keywords

All Science Journal Classification (ASJC) codes

Access to Document

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Cite this